VECoS

THURSDAY, September 15th

8:30 Opening session

9:00-10:00 Invited talk by Erol Gelenbe

Power Aware ICT and Network Management

10:00 Coffee break

10:30-12:30: Stochastic modelling and analysis   

Samira Yessad, Louiza Bouallouche and Djamil Aissani
Proposition and evaluation of a novel routing protocol for wireless sensor networks

Jean-Michel Fourneau and Nora Izri
A tool to model traffic aggregation in networks of reconfigurable optical add/drop multiplexers

Nawel Arrar Remita, Natalia Djellab and Jean-Bernard Baillon
Mx/G/1 retrial queue with impatient batches under low and high intensities of retrials

Hind Castel-Taleb and Nihal Pekergin
Strong and weak orderings for an accurate resource dimensioning

12:30-14:30: Lunch

14:30-15:30 Invited talk by Jean Jacques Lesage

Tailor-made vs. formal languages: how to reconcile effectiveness and rigour of modeling for automation engineering?

15:30 Coffee break

16:00-20:00: Control synthesis and optimization   

Yan Zhang, Béatrice Bérard, Lom Messan Hillah, Fabrice Kordon and Yann Thierry-Mieg
Modeling complex systems with VeriJ

Imed Nasri, Reda Boukezzoula and Georges Habchi
Scheduling and Control Modeling of HVLV Systems Using Max-Plus Algebra

Mohamed Amin Ben Amar, Hervé Camus and Ouajdi Korbaa
A Mathematical Model for Cyclic Scheduling With Limited Work-In-Process and Cycle Time Minimization

Achraf Ben Said, Nejib Ben Hadj-Alouane, Moez Yeddes and Feng Lin
An Iterative Approach for the Satisfaction of Security Using the Intransitive Non-Interference Property

20:00 Workshop dinner

FRIDAY, September 16th

9:00-10:00 Invited talk by Daniel Kroening

Proving Program Termination

10:00 Coffee break

10:30-12:30: Verification   

Alexandre Duret-Lutz
LTL Translation Improvements in Spot

Asma Louhichi, Olfa Mraihi, Wided Ghardallou, Lamia Labed, Khaled Bsaies and Ali Mili
Invariant Relations: An Automated Tool to Analyze Loops

Yannick Kala Konga, Karim Djouani and Guillaume Noel
Formal Modelling and Verification of JXTA peer-to-peer network protocols

Nesrine Harrath, Bruno Monsuez and Joelle Delacroix
Building Systemc waiting state automata

12:30-14:30: Lunch

14:30-16:30: Formal Specification   

Martin Schweikert, Tobias Dornes and Eveking Hans
Using Sequence Diagrams to Specify and to Generate RTL Assertions

Sabine Boufenara, Kamel Barkaoui, Faiza Belala and Hanifa Boucheneb
On Formalizing UML2 Activities Using TPNets: Case Studies

Atef Gharbi, Mohamed Khalgui, Antonio Valentini and Samir Ben Ahmed
Safety Implementation of Adaptive Embedded Control Components

Meriem Belguidoum, Faiza Belala and Fateh Latreche
Toward a rewriting logic framework for safe and distributed component installation

16:30 Coffee break

17:00 Closing session